This invention relates to a nonvolatile semiconductor memory device which is electrically selectable, erasable and programmable.
There has been known a MOS FET type memory cell with a floating gate and a control gate, as shown in FIG. 1. In a semiconductor memory device with a matrix array containing this type of memory cells, data is electrically selectable, erasable and programmable. Each memory cell has a source S and a drain D which are formed on the semiconductor substrate, a floating gate FG formed on a channel region between the source S and the drain D, first and second control gates CG1 and CG2 capacitance-coupled with the floating gate FG, and a program electrode EG for programming the data at the floating gate. The program electrode EG opposes the floating gate FG with a very thin insulating film interposed therebetween to allow a tunnel current to flow.
A matrix array of the memory cells of this type, i.e., 4-bit memory, is shown in FIG. 2. Memory cells M1-M4 are so connected that the drains and the first control gates in the same column are interconnected, respectively, the second control gates in the same row are interconnected, and the sources S and the electrodes EG of all the memory cells are interconnected.
The selective read and write operations of the memory device described above will be described. The memory device is of the N-channel MOS FET type. To access the memory cell M1, the drain D1 and the second control gate CG21 are set at high potential, while the remaining electrodes are set at low potential. When the memory cell M1 is logical "1", a channel current flows into the memory cell M1. When it is logical "0", no channel current flows into this memory cell. The memory cell M1 is in the logical "1" state when no charge is written in the floating gate FG; it is in the logical "0" state when electrons are injected in the floating gate FG and the threshold voltage Vt1 is high and positive. To program or write the contents of the memory cell M1, the first and second gates CG11 and CG21 are set at high potential, while the remaining terminals are set at low potential. In the memory cell M1 only, the potential at the floating gate FG is sufficiently higher than that at the program electrode EG. Alternatively, the first and second control gates CG11 and CG21 are set at low potential, while the remaining terminals are set at high potential to erase the contents of the memory cell M1. In this case, in the memory cell M1 only, the potential at the gate FG is sufficiently lower than that at the electrode EG. Therefore, a tunnel current flows between the floating gate FG and the program electrode EG, thus programming the memory cell M1.
As illustrated in FIG. 3, the potentials at the first and second control gates CG1 and CG2 and the program electrode EG concurrently change at the program start time point t.sub.o.
Since the memory cells are arranged as shown in FIG. 1, the nonvolatile semiconductor memory device is electrically selectable, erasable and programmable. However, the memory device involves the following problems. The potentials at the electrodes and gates of the memory cells are externally controlled, and some time delay is inevitable in transferring signals for such potential control. Therefore, it is difficult to obtain the ideal and simultaneous potential changes as shown in FIG. 3. The first and second control gates CG1 and CG2 are at high potential and the program electrode EG is at low potential. Alternatively, the first and second control gates CG1 and CG2 are at low potential and the program electrode EG is at high potential. In either case, undesirable change of the contents of the memory cells may occur.